The present invention relates in general to data processing and, in particular, to counter-based selection of a victim for replacement from a cache memory.
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be private to or shared by one or more processor cores.
In such systems, the caches of the processing units are typically implemented as set-associative caches, which map cache lines of data to particular congruence classes within the caches based on a predetermined set of bits within the real memory addresses of the cache lines. Each caches typically selects which of the multiple data granules in each of congruence class to evict based on a selected eviction policy, such as most recently used (MRU), least recently used (LRU) or the like.